The present invention relates generally to the field of communications and computing systems and methods for transmitting and exchanging electronic data between two points, and more specifically, to the field of asynchronous transfer mode in data communications for transporting information across a serial bus.
Asynchronous Transfer Mode (ATM) is a protocol-independent, cell-switching network technology that offers high speed and low latency for the support of data, voice, and video and frame relay traffic in real time. ATM provides for the automatic and guaranteed assignment of bandwidth to meet the specific needs of applications, making it ideally suited to support multimedia. ATM also lends itself to upward and downward scaling, making it equally suited for interconnecting local area networks and building wide area networks. ATM based networks may be accessed through a variety of standard interfaces, including frame relay. Although this technology has traditionally been used in local area networks involving workstations and personal computers, it has now been adopted by telephone companies.
ATM is defined in the broadband ISDN protocol at the levels corresponding to levels 1 and 2 of the ISO/OSI model, which are the physical layer and data-link layer. In computer networks, the physical layer is responsible for handling both the mechanical and electrical details of the physical transmission of a bit stream. At the physical layer, the communicating systems agree on the electrical representation of a binary 0 and 1, so that when data are sent as a stream of electrical signals, the receiver is able to interpret the data properly as binary data. This layer is implemented in the hardware of the networking device. The data-link layer is responsible for handling the frames, or fixed-length parts of packets, including any error detection and recovery that occurs in the physical layer.
Voice, video, and data traffic usually are comprised of bytes, packets, or frames. When the traffic reaches an ATM switch, it is segmented into small, fixed-length units called cells. The size of ATM cells is fixed at 53 octets; the cell consists of a 5-octet header and 48-octet payload. The cell header contains the information needed to route the information field through the ATM network.
ATM uses a layered protocol model. ATM has only three layers: the Physical (PHY) layer, the ATM layer and the ATM Adaptation (AAL) layer. The ATM Physical layer currently defines several transport systems, including the Synchronous Optical Network (SONET), T3, optical fiber and twisted pair. There are also ATM physical layer definitions for T1, E1, ADSL, as well as fractional-T1 (i.e., Nxc3x9764 Kbps) interfaces. SONET provides the primary transmission infrastructure for implementing public ATM networks, offering service at OC-1 (51.84 Mbps) to OC-12 (622.08 Mbps). Current definitions of SONET go up to OC 192 (9.952 GBps). SONET facilities have only limited availability to many users, however. Therefore, the user-to-network interface (UNI) outlines the use of DS3 and a PHY layer definition similar to Fiber Distributed Data Interface (FDDI) to provide a 100 Mbps private ATM network interface. The ATM layer provides segmentation and reassembly operations for data services that may use protocol data units (PDUs) different from those of an ATM cell. This layer then is responsible for relaying and routing, as well as multiplexing, the traffic through an ATM network. The AAL resides between the ATM layer and the higher layer protocols and provides the necessary services that are not part of the ATM layer, in order to support the higher-layer protocols.
ATM networks consist of ATM switching systems interconnected by ATM transmission facilities. An ATM switching system is a network element consisting of several physical interfaces, which are tied together via a high speed ATM switching fabric. ATM switching systems perform the function of receiving ATM cell streams on its interfaces, and independently routing each cell to a pre-defined output interface based on its input port, ATM cell header, and associated connection. Cells are routed through the ATM switching system (and network) along a fixed path through the network based on a specified connection and the connection policy attributes. Policy attributes establish certain criteria for the connection which become significant during periods of congestion. ATM switching systems employ buffering and scheduling techniques to minimize traffic loss and ensure connections are properly serviced based on policy attributes during periods of congestion.
Since traffic through an ATM network is asynchronous, it is very possible that cells arriving from a number of different physical interfaces at the same time are all directed to the same physical egress port. The event of scheduling cells from one or more input ports whose combined input rates exceeds the intended link""s output rate, results in link congestion. ATM switching systems employ buffering to absorb traffic bursts.
A typical ATM switching system architecture has multiple physical interfaces interconnected via a high speed switching fabric. A typical switch can range in capacity from (16-160) 155 Mbps interfaces and in traffic capacity of 2.5 Gbps to 25+Gbps. ATM layer devices are typically designed to operate at either 155 Mbps or 622 Mbps. The ATM UTOPIA interface partitions the ATM switching system into a PHY layer and ATM layer. The ATM layer is typically associated with the high speed ATM switching fabric. The PHY layer is associated with the physical interface. The PHY layer typically transfers asynchronous cell streams from the ATM layer and adapts them onto the physical transmission medium. The ATM layer and its interface to the switching fabric typically operates at much higher transfer rates than the PHY layer. With the PHY layer having minimal buffering (2-4 cells), and the significant rate mismatch between the PHY and ATM layers, requires an asynchronous transfer control handshake between the ATM/PHY layers of the switch. Consequently the ATM layer typically performs the required cell buffering, traffic scheduling, and congestion control.
The UTOPIA protocol defines a standard interface between the ATM and PHY layers of an ATM switching system. This interface standard allows ATM switch fabrics supplied by 1 device manufacturer to interoperate with PHY devices from another manufacturer. This provides multiple technology supplier alternatives to ATM switch manufacturers. Aside from the UTOPIA standard, there are really no other xe2x80x9cstandardxe2x80x9d interfaces between components in an ATM switching system. For the majority of ATM switching systems, the switch fabric portion of the design is a highly proprietary multi-device switching architecture from a single device supplier.
Since ATM switching fabrics are architected and structured to provide the interconnection of a large number of high bandwidth links, the ATM layer devices are typically designed to support 155 Mbps and now more commonly 622 Mbps interfaces and data rates. The ATM layer devices are fairly costly due to their bandwidth performance, traffic processing complexity, and ability to support large amounts of high-speed cell buffers. They typically have UTOPIA interfaces operating at 25 Mhz or 50 Mhz. What""s worse, the 50 Mhz MPHY UTOPIA timing specifications have little to no timing margin, limiting the UTOPIA bus to operation on a single PCB (printed circuit board) or circuit pack within the system. This requires the ATM layer device and its associated PHY""s to reside on the same board. This physical restriction really limits the ATM layer""s ability to be shared across the maximum number of PHY devices in a system.
For example, a 622 Mbps ATM layer device can support over 300 2.048 Mbps E1 PHY interfaces. The real-estate requirements for 300 E1 interfaces is likely to be a factor of 10 higher than would practically fit on a single PCB in a system. In fact, a single 622 Mbps ATM-layer device would likely support an entire system, where the physical interfaces are distributed across many PCB""s in the system.
Typically, ATM PHY-layer devices with ATM ATM-layer devices reside on the same printed circuit board, and are interconnected by a 16/32 data bus and several control signals to exchange ATM cells across the interface. When PHY/ATM layer devices are on the same printed circuit board (PCB) there is no overhead in connecting these devices using the standard UTOPIA interface. However, if the PHY/ATM layer devices reside on different PCBs, the number of signals required to interconnect the PHY/ATM layer devices the standard UTOPIA interface may be impractical, limit the scale of the system, bear a heavy cost burden, or may not even be possible due to timing requirements. Abstracting the UTOPIA interface over an adjoining bus using intermediate circuits enables the timing requirements to be satisfied. In addition, by reducing the number of signals required to extend the UTOPIA interface between multiple PCBs reduces the cost, complexity, and allows a greater number of these interfaces to be extended in the system.
The number of signals required to extend the UTOPIA interface across PCBs can be dramatically reduced by transporting the data and control information serially. This is of particular significance when a large number of PHY interfaces connect to a single ATM layer interface across multiple PCBs in a product or system. While there exists implementations for transmitting ATM cells across various non-UTOPIA bus interfaces, current implementations (prior art) are methods for interconnecting the multiple components comprising the ATM switch fabric section of the ATM switching system. The distinctive characteristic of prior art is that these devices are intended to perform the cell buffering, cell header translation, cell processing, cell scheduling, routing and cell discard functions within a larger switching system. Each instance of the device is connected to the rest of the fabric via interfaces unique to that manufacturer""s chipset. The interconnection is typically over high bandwidth interfaces typically 155 Mbps/622 Mbps or greater. And finally, the PHY interfaces reside on the same PCB or module as their associated ATM-layer slice of the switch fabric. In various implementations where ATM data is exchanged over backplane buses, control signals are transported xe2x80x9cout-of-band.xe2x80x9d Out-of-band control signaling requires extra electronics to handle the signaling band and may not be practical or cost effective.
There is, therefore, a need in the industry for a system and method addressing these and other related and unrelated problems.
Certain objects, advantages and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
The system of the present invention extends the basic architecture of the ATM switching system by providing a method for exchange of UTOPIA data and control information between the ATM and PHY layers of a switching system across a secondary transmission bus. The seconday transmission bus allows the ATM and PHY layers to be located on different PCBs in an ATM switching system which due to proximity or other restrictions makes it impractical to directly connect these entities using the UTOPIA interface. The secondary transmission bus requires a device on both sides of the interface to provide proper handshaking and meet timing requirements with the respective ATM layer and PHY layer devices. There would typically be one interface device located on the same PCB with the ATM layer and one interface device with the PHY layer. The interface devices are capable of transporting data between ATM layer and PHY layer devices. The interface devices also relay principal interface control signals and status indications, in a manner consistent with ATM layer and PHY layer control requirements. Primarily, this involves controlling the asynchronous transmission of cells across the data interface, which includes indicating when data being transmitted across the bus are valid or invalid (i.e., Idle), and where cells begin or end. It also involves the PHY layer""s ability to indicate when it is able to accept cells from the ATM layer, and indicate when it has received cells which are ready to be transferred to the ATM layer (i.e., flow control). In a Multi-PHY configuration, the bus also provides a means for the above transfer control signaling for each associated PHY of the Multi-PHY.
The flow control mechanisms set forth in this invention minimize the amount of buffering required in the PHY layer device, as well as the ATM layer serial, and PHY layer serial interface devices (1-4 cells per device). Not only does it minimize the buffer requirements of these blocks, but it places the buffering and traffic management complexity in the ATM layer where it is typically found. Without employing these flow control techniques, the interface devices, and/or PHY device would become much more complex. If neither flow control, nor increased complexity in these devices is employed, the system will experience significant traffic loss during periods of congestion.
While there are many different bus designs which address the above invention, the intent of this disclosure is to detail a particular preferred bus implementation and identify specific techniques and methods enabling the preferred bus implementation to support the invention.
A system where a large number of PHY devices share the ATM layer device typically involves the interconnection of many PCBs using high speed backplane (system) buses. While system buses interconnecting the various PHY layer PCBs with the ATM layer PCBs can either be shared buses or point-point (serial) buses, point-point serial buses are illustrated in this invention. Methods and topologies defined for the point-point serial case, can also be shown to apply to the shared bus case. The reference to serial bus, also includes (n bit) wide point-point data buses.
Using the method and protocol of the present invention, the UTOPIA bus can be extended over a serial bus, reducing the PCB-PCB interface to as few as two data signals, and a clock. This minimizes the number of signals required to interconnect the ATM layer and multiple PHY layers in the system. Optimally, in-band signaling uses not only the same physical path as the data it serves, it also uses the same operating frequency as the data signals that are carried. The UTOPIA bus width can be increased by (n*2) data signals depending on the required bus bandwidth. Depending on the level of complexity required over the UTOPIA bus, protocols of varying complexity may be employed to provide the serialization and control of traffic.
According to the preferred embodiment, asynchronous cell transmission is accomplished without flow control, where minimal control information is required between the ATM-PHY layer interface.
According to another preferred embodiment, asynchronous cell transmission is accomplished with cell level flow control to compensate for data congestion at the receiver. Cell level flow control enables a receiver to signal to its remote transmitter to stop sending cells until the receiver is ready to accept them again. In cell level flow control, cell transfer is suspended following transmission of the last octet of the cell.
According to yet another preferred embodiment, asynchronous cell transmission is accomplished with octet level flow control. Octet level flow control introduces the added complexity that either the PHY or ATM layer interface have the ability to send a control signal indication to the other end at any time. In octet level flow control, cell transfer may be suspended prior to transmission of the last octet of the cell. Data can be suspended/resumed at any time.
It is therefore the object of the present invention to provide a protocol for transmitting signaling information across a serial bus both in-band and out-of-band. In-band signaling consists of encoding transfer control signals and indicators in the data bit stream. Out-of-band signaling is where transfer control signals and indicators are communicated on signals other than those carrying the data bit stream.
Another object of the present invention is to provide a protocol for transmitting signaling information xe2x80x9cin-bandxe2x80x9d across a serial bus, thereby reducing the UTOPIA bus to as few as two data signals and a clock signal.
Another object of the present invention is to provide a cost-effective, scalable means for sharing a large number of PHY interfaces across an ATM layer interface. The ability to share large number of PHY interfaces across an ATM layer interface is typically required in broadband access multiplexers, concentrators, or ATM network access devices, such as DSLAMs. An ATM layer device operating at 622 Mbps, can theoretically support over 300 2.048 Mbps PHY interfaces.